It is a generally desirable goal in semiconductor fabrication to reduce the size of semiconductor devices. This holds true for semiconductor memory devices such as Dynamic Random Access Memory (DRAM) devices. As semiconductor memory device dimensions continue to shrink, and the corresponding density continues to increase by a 4.times. rule, the storage cell gets increasingly smaller while the required storage charge remains about the same. Conventional oxynitride (N/O or O/N/O) dielectrics have a relatively low capacitance per unit area (.about.7.7 fF/um2, for an effective oxide thickness of 4.5 nm) that limits the storage capacity because of potential high tunneling leakage. To combat this problem, various area enhancement technique have been proposed, including hemispherical grain (HSG) rugged poly, disks, fins, and corrugated cylindrical cell (CCC). However, these area enhancement techniques have inherent limitations.
The HSG technique requires complicated deposition processes within a narrow temperature window. Storage cells that incorporate fins, disks, and CCC formations are primarily composed of multiple horizontal fins. As the storage cell size is further decreased, the fins add less surface area than vertical sidewalls. Furthermore, the typical fin-type structure fabrication is not a robust manufacturing process, and results in a storage cell that is less mechanically stable, especially during oxide removal between horizontal fins and particle removal.
In another attempt to overcome the limitations of conventional oxynitride dielectrics, high dielectric constant materials, including Ta.sub.2 O.sub.5, Ba.sub.1-x Sr.sub.X TiO.sub.3 (BST), SrTiO.sub.3, and Pb.sub.1-x Zr.sub.x TiO.sub.3 (PZT), have been proposed as storage dielectrics due to their high capacitance per unit area. The high capacitance per unit area could theoretically allow use of a simple stacked cell storage cell structure. However, high dielectric constant materials are new to semiconductor fabrication and several obstacles exist to implementation in semiconductor fabrication, including contamination to transistors, robust deposition process development, etching of the new materials, integration experience, and reliability.